Can AI design a chip?

Partly, and the honest answer depends on which part. Reinforcement learning systems now do macro placement, the step that decides where large blocks sit on the chip canvas, at a quality Google says matches or beats its own physical design team, a claim outside researchers have disputed and Google's authors have defended in print, and Google reports using its AlphaChip system on layouts for TPU v5e, v5p and Trillium and for its Axion server CPUs. That is one step in a pipeline that runs from architecture through logic design, verification, physical design and sign-off. No system today takes a specification in one end and produces a manufacturable design out the other without expert humans in the loop. Ricursive Intelligence describes exactly that end-to-end capability as a later phase of its roadmap, not as something it ships now, which is a fair reading of where the field is.

Can AI replace chip designers?

Not on current evidence, and the shape of the change matters more than the headline. The two steps that consume the most time, physical design and design verification, each absorb up to a year and hundreds or thousands of engineers, so even a partial automation removes an enormous amount of labor from the critical path. What it removes first is the iteration: the many-day tool runs that a human waits on, rather than the judgment about what to build. The realistic near-term picture is fewer engineers spending far less time waiting, with the architecture and specification decisions still human. Worth noting that the strongest claims in this area are contested, so treat any vendor promise of full automation as a claim to verify on your own designs.

How much does it cost to design a chip?

At a leading-edge process node, hundreds of millions of dollars, though the published figures deserve skepticism. The most widely cited estimate, from International Business Strategies in 2018, put the design cost of a 5nm chip at $542.2 million. SemiEngineering argues those headline numbers overstate what real programs spend, because no chip is ever designed from a blank sheet of paper: teams reuse blocks, tooling and verification suites from previous generations. A more useful way to hold the number is that a leading-edge design is a multi-year, multi-hundred-person commitment, which is precisely why compressing the two longest steps is worth a great deal of money and why the category attracts the funding it does.

Which companies are leading in AI chip design?

The incumbent electronic design automation vendors moved first and have the distribution: Synopsys ships DSO.ai for design space optimization and Cadence ships Cerebrus for the same class of problem, both of which put reinforcement learning inside tool flows that chipmakers already use. Google produced the most cited research result with AlphaChip and has applied it to its own TPU and Axion silicon. NVIDIA has published ChipNeMo, a family of models adapted to chip design tasks such as answering engineering questions and writing scripts. Ricursive Intelligence is among the best funded of the startups attacking the full workflow rather than one step of it. The useful distinction when evaluating any of them is whether the claimed gain was measured on designs an outside party can inspect.

AI Chip Design: When the Loop Closes

AI chip design means handing the slowest parts of building a semiconductor, placing and routing billions of components and proving the logic is correct, to machine learning systems rather than to human engineers driving commercial tools. It deserves a founder's attention even if you will never tape out a chip, because it is the clearest working example we have of AI improving the substrate that AI itself runs on.

Anna Goldie and Azalia Mirhoseini co-created AlphaChip at Google, the reinforcement learning system that generates chip floorplans, and left to found Ricursive Intelligence, where Goldie is CEO and Mirhoseini is CTO. Goldie did her PhD at Stanford, co-founded the ML for Systems team at Google Brain, worked on Constitutional AI at Anthropic, and was a senior staff research scientist at Google DeepMind, where she worked on Gemini. Mirhoseini co-founded that same team at Google Brain, was also at Anthropic, and is now an assistant professor of computer science at Stanford, where she runs a lab on scalable and self-improving AI systems.

They presented the company in a talk at Sequoia Capital, and it is unusually specific about where the time actually goes. The company has raised $335 million, a $35 million seed followed by a $300 million Series A at a $4 billion post-money valuation led by Lightspeed, with NVIDIA's venture arm NVentures, DST Global, Felicis and Sequoia among the participants.

Goldie states the thesis in one line: "chips are the fuel for AI," so you use AI to design them and "close this recursive self-improving loop between AI and its physical substrate." That sentence is the reason this talk is worth reading as a founder rather than as a semiconductor person. It is a specific, testable claim about when a compounding loop is available, and the story of how it has gone so far contains the warning as well as the promise.

The two chip design jobs that take a year

Goldie names two long poles in the existing process. Physical design is "placing the billions of standard cells" or transistors and routing the connections between them onto a chip canvas. Design verification is proving the logic of that chip is correct. Her summary of both: "Each of these can take up to a year and involves hundreds or thousands of human experts."

Hold that next to the money. The most cited estimate of leading-edge design cost, published by International Business Strategies in 2018, put a 5nm chip at $542.2 million. SemiEngineering makes the fair objection that such figures overstate real programs, since no chip starts from a blank sheet of paper and teams inherit blocks, tools and test suites from the last generation. Take the criticism and the number is still enormous: a multi-year commitment from hundreds of specialists, on a schedule where arriving late can cost more than the design did.

That is the shape of a genuine opportunity, and it is worth naming the shape rather than the industry. Two steps, each measured in expert-years, each sitting on the critical path of something the buyer desperately wants sooner. Most founders never map their customer's process with this much precision. Map it. Where are the two long poles, how many people stand under each one, and what does one week of delay cost the person writing the check?

They rebuilt the tools before pointing AI at them

This is the most transferable decision in the talk, and it is a sequencing decision rather than a modeling one.

Mirhoseini describes the traditional flow as phases run by human experts working with commercial tools that, in her words, sometimes take days to run for a single iteration of an optimization. The obvious move, the one most teams make, is to put a model on top of that flow and let it drive the existing tools. Ricursive did the opposite. The stated approach is to first redesign the tools themselves, "make them 100,000x faster," and only then use them with AI, because "our AIs really like fast iteration loops."

The demo they show is a static timing analysis engine, one of the harder pieces of physical design. Their claim is that it "correlates with the commercial tools very high fidelity" while running about a thousand times faster. The point of the speed is not the speed. It is that a fast, trustworthy evaluator turns into a reward signal an optimizer can call a very large number of times, which is what makes the outer loop work at all.

The generalization is blunt. If your inner loop takes a day, an agent gets a handful of attempts before your runway or your patience ends. If it takes a second, it gets a hundred thousand. Model quality is very often downstream of iteration speed rather than the other way around, and teams routinely spend months on prompts and fine-tuning when the binding constraint was that their evaluation harness took four hours to run. The same logic is why LLM evaluation deserves engineering attention early: the eval is not paperwork, it is the thing your improvement loop consumes.

Dylan Patel of SemiAnalysis makes the compounding version of this argument about layers rather than loops. Optimizing the model, the hardware and the layer between them separately gives you gains that add up politely. Doing them together is different: "instead of being multiplicative to 8x, it's actually 100x because you've optimized across all three layers." Ricursive is making that bet inside a single company, which is also why it is a capital-intensive one.

A closed loop is only as good as the number it optimizes

Here is the part a founder should read most carefully, because it is the part that has actually been tested in public.

AlphaChip was published in Nature in June 2021 as A graph placement methodology for fast chip design, with Mirhoseini and Goldie as its first two authors. Google reports using it on layouts for three TPU generations, v5e, v5p and Trillium, and for Axion, its Arm-based data center CPUs, and says MediaTek adopted and extended the method. In the talk, Goldie describes the reinforcement learning agent as "generating superhuman chip layouts."

Those claims have been disputed at length. Researchers at UC San Diego led by Chung-Kuan Cheng and Andrew B. Kahng re-implemented the method and reported that it did not outperform existing techniques, including a stronger simulated annealing baseline and a commercial place-and-route tool. A separate meta-analysis by Igor Markov went further, arguing the paper's integrity was undermined by errors in conduct, analysis and reporting. Nature added an editor's note to the paper in September 2023 saying the performance claims had been called into question, then removed that note in September 2024, closed its investigation after a review by its editors and a panel of reviewers, and published a clarifying addendum. The critics maintain their technical objections were never answered. Goldie, Mirhoseini and Jeff Dean published a detailed rebuttal, "That Chip Has Sailed", arguing that the replication used far less compute than the method requires and skipped key training steps, and pointing to the production adoption as the answer. No one outside Google has been able to rerun the original evaluation, because the TPU blocks it used are proprietary. The public re-runs use open benchmarks instead, and the two sides disagree about whether those are representative.

Do not read that as a verdict on who is right. Read it as a structural lesson, because the structure is what repeats in your company.

A self-improving loop optimizes whatever number you hand it, and the number is the entire product. If your only proof runs on data nobody outside can touch, then no customer can distinguish a real gain from a favorable setup, and, more uncomfortably, neither can you. Teams in that position are not usually lying. They are running an optimizer against a metric they also control, which is how a benchmark quietly turns into a mirror.

Notice that Ricursive's own framing answers this directly. The claim about the timing engine is not that it beats the commercial tools, it is that it correlates with them at high fidelity and runs a thousand times faster. That is the right order: reproduce the incumbent's number on the incumbent's terms first, then win on speed. It is a claim a skeptical buyer can check.

The security instinct applies cleanly here. You would not let the team that wrote the code own the only test of whether it is secure, and for the same reason you should not let the team that owns the model own the only benchmark it is judged on. Build the evaluator so that someone who wants you to be wrong could run it, which is the same discipline that makes AI reliability claims survive contact with a customer.

Designless is the business model bet

The company describes three phases, and they escalate in a way worth noting.

Phase one is acceleration: help existing chipmakers get to market faster and cheaper. Phase two is a platform. Take a workload as input, design an architecture that accelerates it, and carry the design all the way to the format that goes to the fabs, which would open custom silicon to companies that could never staff hundreds of chip experts. Phase three is vertical integration, and Goldie puts it as a question: if you can design high performance chips quickly, "why not build our own chips?" and train your own models on them.

Mirhoseini gives the model a name by analogy. Fabless design became possible once foundries like TSMC let companies design chips without owning a fab, which is the arrangement that made NVIDIA and Apple possible. She calls the next step "designless, just like fabless," with Ricursive as the platform, and the outcome she wants from it is "this Cambrian explosion of chips," many more designs tuned tightly to specific workloads.

The obvious objection came up in the Q&A: does the economics work, when custom silicon has always meant spreading a fixed design cost over enough volume to justify it. The answer given was that compute becomes a knob you can turn, scaling it to cut design time and raise performance, and that at the scale AI workloads now run, "Even a 1% improvement in a chip that serves a frontier model" is worth having. That is a real argument at frontier scale and a much weaker one at small volumes, which is worth holding onto rather than waving through.

The pressure behind all of it is physics. Naveen Rao, who co-founded Nervana and later led AI at Databricks, says "there is a thermodynamic limit to intelligence per watt," and the human brain, at roughly 20 watts, shows how far current computing sits from it. When general purpose hardware stops delivering easy gains, specialization is one of the few knobs left. That is the demand-side case for both custom silicon and cheaper design, and it is the same pressure showing up in how founders now evaluate an inference chip or decide whether they need a GPU cluster at all.

When the machine is right and it looks wrong

One detail from the Q&A is worth more than its length.

Asked what the model's placements look like, the founders described curved, organic shapes. Human experts, as the answer put it, "tend to make these very aligned, regular-looking placements," while the generated ones are irregular, "which minimizes wire length, improves performance," and it was genuinely shocking to physical design engineers the first time they saw them.

That is the adoption problem in miniature, and it is not an accuracy problem. A better answer that violates a professional aesthetic reads as a mistake to the exact people whose sign-off you need. Every team shipping AI into expert hands meets this: the recommendation is correct, the expert cannot see why, and the expert is the one with veto power. The cost is not in the model, it is in the explanation you ship next to the output, and teams routinely underestimate how much of the product that is.

What AI chip design teaches founders who will never build a chip

The pattern generalizes, but only under conditions worth stating plainly, because build-a-self-improving-loop is advice that gets repeated far more often than it is earned.

The loop needs an objective, cheap, trusted signal. Chip layout has one: wire length, timing, power, area are numbers, not opinions. Most business processes do not have this, and pretending otherwise produces a loop that optimizes a proxy until the proxy breaks. Before you design the loop, ask what the number is and who would accept it.
Own the evaluator before you own the model. The durable asset in Ricursive's story so far is a fast timing engine that agrees with the tools the industry already trusts, not a model checkpoint. Evaluators age well. Model weights age in months.
Iteration speed is a product decision, not an infrastructure chore. A hundred thousand fold speedup in the inner loop changes what the outer loop can be. Decide early what your inner loop is and what it costs per turn, and treat that number as a roadmap item.
Compounding requires the output to feed the input. AI designing chips that train better AI is a real cycle. Most things sold as flywheels are not: the output goes to a customer and never returns as an input. If your loop does not close, you have a good product, which is fine, but price and plan it as one. The wider version of this argument, and the places it does hold, is what we cover in self-improving AI and across the AI for startups pillar.

None of the four require a fab. All four are decisions you can make this quarter about a much smaller product.

What to do this week

Name your inner loop and time it. Write down the single cycle your team repeats when improving the product: change, evaluate, learn. Measure how long one turn takes end to end, in minutes.
Compute the turn budget. If that loop runs overnight, you get roughly 250 turns a year. Decide whether the thing you are trying to learn is learnable in 250 attempts. If not, the loop is the problem, not the model.
Find the tool in the middle that is slow, and ask whether it can be rebuilt rather than tolerated. Ricursive's entire bet is that the evaluator was the constraint. Check whether yours is a service call, a test suite, or a human review queue.
Write down your benchmark and hand it to someone who wants you to be wrong. If they cannot run it, it is not a benchmark, it is a demo. Fix that before a customer finds it.
Check which of your metrics you both optimize and own. Any number that is scored by the same system that produces it needs an external anchor, even a rough one.
Pick one expert-facing output and write the explanation that goes beside it. If your system is ever right in a way that looks wrong, you will need it, and you will not have time to write it then.

Turning these loops into something your team runs every week without you is what we teach in AI Operating System for Startups.

Sources

AI That Designs Its Own Chips: Ricursive's Anna Goldie and Azalia Mirhoseini (Sequoia Capital), the talk this article is built on. All quotations attributed to Goldie and Mirhoseini come from this presentation and its Q&A; where the Q&A does not identify which founder is answering, the answer is attributed to them jointly.
Why Hardware-Software Co-Design Is AI's Real 100x (Sequoia Capital), Dylan Patel of SemiAnalysis, for the argument that gains across model, hardware and the layer between them multiply rather than add.
Why the Brain Computes 1,000,000x More Efficiently Than A GPU (Sequoia Capital), Naveen Rao, for the thermodynamic limit on intelligence per watt and the 20 watt comparison.
Ricursive Intelligence funding and roles: the company's $300 million Series A announcement gives the $4 billion post-money valuation, the Lightspeed lead, the participating investors and the co-founder titles; TechCrunch reports the $35 million seed and the $335 million total. The company describes its own mission on ricursive.com.
AlphaChip production use: Google DeepMind's September 2024 post names TPU v5e, v5p and Trillium, the Axion CPUs, and MediaTek's adoption. The original paper is A graph placement methodology for fast chip design, Nature volume 594, pages 207 to 212.
The benchmark dispute: the UC San Diego assessment "An Updated Assessment of Reinforcement Learning for Macro Placement" by Chung-Kuan Cheng, Andrew B. Kahng and colleagues; the separate meta-analysis "The False Dawn: Reevaluating Google's Reinforcement Learning for Chip Macro Placement" by Igor Markov, which is where the conduct and reporting allegations come from; and the authors' response "That Chip Has Sailed: A Critique of Unfounded Skepticism Around AI for Chip Design" by Anna Goldie, Azalia Mirhoseini and Jeff Dean, which rebuts the two separately. Wikipedia's AlphaChip article summarizes the sequence, and Nature's own addendum accompanied the removal of the editor's note.
Chip design cost: "What Will That Chip Cost?" (SemiEngineering) reports the International Business Strategies estimate of $542.2 million for a 5nm design and makes the case that published figures overstate real programs.
Founder backgrounds: Anna Goldie's site and Azalia Mirhoseini's Stanford faculty page.
Tools named in the FAQ: Synopsys DSO.ai, Cadence Cerebrus, and NVIDIA's ChipNeMo research.